In recent years, the microfabrication of an element or a transistor is progressing with high integration of LSI (Large Scale Integration). However, it is faced with the physical limit of an element or a transistor in conventional ultra-fine processing technology. Therefore, new transistor structure except for a conventional planar type transistor is developed. The FIN type transistor which is a transistor of three dimensional structure is in the developed new transistor structure. The FIN type transistor is described, for example to Patent Reference 1.
On the other hand, in the SOI (Silicon on Insulator) device, on a Si substrate, an insulator and single-crystal Si (SOI layer) are laminated, and the transistor is formed on an SOI layer. In this SOI device, when it has the hybrid trench isolation which used partial isolation and full isolation together in element isolation, the high speed and low power operation of the SOI device concerned are attained. Since the substrate potential floating effect can be inhibited according to substrate potential fixation structure in an SOI device, application is also possible to an analog circuit, a digital circuit, etc.    [Patent Reference 1] Japanese patent laid-open No. 2005-019996